Terminology and defining authorities.
Core-2 Glossary
Status: explanatory index; normative definitions live in the linked authorities
| Term | Meaning | Authority |
|---|---|---|
| hardware domain | spatial structure and continuous circuit evolution; callable tag 5 | Edition |
| physical model | non-callable mathematical model of geometry, fields and laws | Physics |
| authoring modality | interpreted or compiled intent, independent of timing discipline | Edition |
| component | finite elaborated hierarchy with a typed port contract | Hardware |
| port / net / driver | boundary connection / connected signal / producer of its value | Hardware |
| elaboration | finite construction of circuit structure before evolution | Hardware |
| discipline | combinational, clocked, asynchronous or intrinsic region laws | Hardware |
| Logic X / Z | indeterminate logical value / high-impedance logical state | Hardware |
| reference value | immutable bounded Bit/Logic data operated on without starting a circuit session | Hardware |
| finite resolution fold | explicit four-state table exhaustively checked for closure, identity, associativity and commutativity | Hardware |
| CDC | crossing between clock domains or from asynchronous inputs | Hardware |
| isochronic fork | identified branches with a declared timing/skew obligation | Hardware |
| intrinsic | behavior whose validity depends on the measured physical substrate | Hardware |
| strong / weak form | pointwise differential relation / variational relation over test functions | Physics |
| field space | field location, rank/frame, continuity and test/trial restrictions | Physics |
| canonical mesh | declared geometry/topology authority, distinct from a solver mesh | Physics |
| constitutive law | material response relation with a stated validity range | Libraries |
| bridge | typed transfer law across disciplines, clocks or digital/physical models | Bridges |
| reference bridge definition | source-owned component with checked endpoint roles and a versioned digital transfer constraint; not execution or device evidence | Hardware |
| crossing history | bridge provenance retained through combinational and register dependencies when checking an unproved coherent join | Hardware |
| guarded CDC step | fresh model-scoped Simulator operation publishing candidate register, bridge and trace state atomically | Hardware |
| sampled / post reset | reset seen by state on an edge / reset after the release pipeline advances on that edge | Hardware |
| collecting / sealed async value | immutable reference phase accepting one complete drive snapshot / awaiting the next simultaneous event commit | Hardware |
| async obligation reference | identity retaining a source timing, hazard or environment obligation; not its proof or execution admission | Hardware |
| source async law | checked versioned timing/protocol/fork definition with resolved bindings, separate from execution and physical evidence | Hardware |
| async reference horizon | finite capability-guarded evolution through all due events and microsteps, with atomic circuit/queue/trace publication and explicit interval choices | Hardware |
| realization binding | owned preparation record pinning an actual checked software contract, baseline body and native implementation model; not observation admission or equivalence evidence | Realizations |
| scalar observation map | explicit, total fixed-width software parameter/result to combinational root-port projection, with separate pending proof obligations | Realizations |
| source scalar relation | named component constraint proposing an original software symbol and explicit port encodings; independently checked through the scalar mapping gate | Realizations |
| typed realization proposal | owned canonical binding and observation-map record rechecked against actual dependencies; still awaiting equivalence/evidence and promotion | Realizations |
| realization | checked refinement edge preserving the original contract | Realizations |
| observation map | relation from implementation traces/results to contract observations | Realizations |
| claim / evidence | required relation / bounded, provenance-bearing support for it | Realizations |
| SolverPlan | inspectable proposed numerical implementation of a model analysis | Solver plans |
| promotion | atomic selection of an admitted realization; separate from configuration | Realizations |
| checked async-to-clock composition | separately admitted atomic reference horizons over clockless state, named clocks and actual CDC bridges; not implicit reverse crossings or physical evidence | Hardware |
| retained-word endpoint reset | independent local reset/recovery while bridge-owned words and protocol metadata survive; an explicit target-retention obligation, not implicit cancellation | Hardware |
| retained source law | checked word bridge definition whose endpoint reset modes come from actual clock bindings and whose retention requirement does not grant execution or target proof | Hardware |
| retained clocked profile | distinct model-scoped Simulator execution preserving bridge-owned words and acknowledgements across independent endpoint reset/recovery, with atomic publication and separate trace identities | Hardware |
| retained composed horizon | atomic async/clocked evolution mixing source-bound retained words and legacy point-aware bridges without changing either law or inventing clock edges at microsteps | Hardware |
| target artifact | target-specific netlist, bitstream or other materialized output | Artifacts |
| physical instance | enrolled individual device, distinct from its part family | Adapters |
| indeterminate action | a physical effect may have occurred without a reconciled receipt | Boundaries |
| ZLM3 | new checked-artifact family with staged binary encodings | Artifacts |
| logical-record normalization | bounded typed structural validation and canonical JSON ordering; not execution admission | Artifacts |
| transport byte pin | external SHA-256 of exact file bytes; not a semantic identity, signature, proof or capability | Artifacts |
| identity frame | exact versioned domain/format/payload preimage; integrity alone does not admit its semantic subject | Artifacts |
| component semantic payload | canonical checked public specialization/ports or full combinational circuit body, excluding source locations and simulation resource limits | Artifacts |
| component-scoped interface | canonical contract-only interface/5 checked against a full expected identity; no implementation, evidence approval or live authority | Artifacts |
| checked-context semantic projection | component semantic/5 with separate contract/body identities, verified against an actual checked component; contains private circuit structure but grants no execution | Artifacts |
| realization evidence context | exact baseline body and native execution-model pins, separate from the portable logical refinement edge and still mandatory for dependent proof reuse | Artifacts |
| scalar claim projection | public interface/5 exposing a proposed checked scalar relation without its baseline/native evidence context; semantic/5 additionally binds that context, but neither proves the claim | Artifacts |
| inherited software projection | opt-in scoped /5 inspection preserving exact Core-1 declarations, original identity formats and required capability names; not software recompilation or hardware lowering | Artifacts |
| finite scalar reference evaluation | exhaustive supported-input comparison between actual software and the guarded reference simulator, with distinct fail/unsupported/inconclusive outcomes; not independently attested target proof or promotion | Realizations |
| combinational netlist | bounded derived two-state signal/node/driver IR with a distinct implementation identity and explicit width boundaries; not target synthesis or promotion | Hardware |
| scalar datapath proposal | bounded non-trapping Algorithm leaf translated to source-authored-gate checked hardware, typed realization and netlist; unchanged software contract, separate implementation and unattested lineage, no proof or authority | Realizations |
| checked scalar-local report | read-only exact fixed-width local typing from checked declarations or bounded initialized straight-line reconstruction; original contract/body pins, no execution or proof authority | Realizations |
| netlist source map | separately owned, unattested file-label/offset mapping to canonical netlist IDs; not source-content authentication or a semantic hash input | Artifacts |
| point-aware CDC value | separately identified immutable transfer wrapper ordered by timestamp/microstep, preserving tick apertures and edge-only progress without granting mixed-region execution | Hardware |
| structural artifact | validated non-executable record transport, separately advertised from executable admission | Artifacts |
| record-layout registry | ordered closed field/type/tag vocabulary shared by logical inspection and future binary minors | Artifacts |
| ZL512 | separately versioned 256 software + 128 hardware + 128 physics corpus | Corpus |