Primary references for HDL, async, physical and intrinsic design.
Core-2 Prior Art
Status: informative; references inform the design, not source compatibility
The language should acknowledge that Verilog/SystemVerilog and VHDL can describe concurrent and asynchronous behavior: they do not require one global clock. SystemVerilog’s simulation, assertions and mixed design abstractions are documented by IEEE 1800-2023, and VHDL by IEEE 1076-2019. Core-2 specifies its own event and admission laws and promises no source compatibility.
CIRCT’s hardware dialect rationale separates modules, instances and shared types from higher-level combinational and sequential operations. Core-2 likewise makes structure and evolution explicit, while keeping its checked identities and realization contracts independent of a particular downstream IR.
ACT’s language documentation describes communicating hardware processes, handshaking expansions and production rules at different levels of circuit description. This informs explicit async assumptions and refinement across abstraction levels. It does not justify treating every asynchronous circuit as handshake-based. The professor’s language referred to as MAGIC remains an unverified attribution; no syntax or historical claim is assigned to it until a specific source is identified.
Modelica 3.6’s equation specification provides prior art for declarative equation systems rather than imperative assignment. Core-2 adds its own mesh, field, realization and numerical evidence contracts; it does not claim that arbitrary PDEs are well-posed or solvable.
Adrian Thompson’s An Evolved Circuit, Intrinsic in Silicon, Entwined with Physics is a primary experimental account of evaluating evolved configurations on an FPGA. It describes a clockless tone-discrimination experiment and examines physical properties beyond a conventional logic abstraction. The publication is identified by DOI 10.1007/3-540-63173-9_61. Core-2’s intrinsic profile is a design response: retain device, environment, placement/routing and measurement identity. It does not generalize that experiment into a universal FPGA speed, portability or reliability claim.